(1) Field of the Invention
The present invention relates to a process for forming a buried drain or collector region in monolithic semiconductor devices comprising an integrated control circuit and one or more MOS or bipolar power transistors with vertical current flow integrated in the same chip.
(2) Description of the Related Art
Association in the same chip of power transistors with vertical current flow and an integrated control circuit provides a very compact and efficient device which is advantageous as compared with separate components.
A recurring problem in providing such devices is minimization of the differences S between the distance 1 separating the drain or collector junction of the power transistor from the substrate and the distance d separating said substrate from the lower margin of the isolation region of the integrated control circuit (for reasons which are explained below).
To minimize said differences S there is usually provided a buried drain region (or a buried collector region for bipolar devices) by means of selective implanting of phosphorous (a highly diffusive dopant) on the substrate. During the epitaxial growth and the subsequent diffusions the phosphorous rises to the top of the chip faster than the antimony with which the substrate is doped.
This technique has considerable drawbacks. A first problem consists of the large tolerances which must be respected for the layout rules because of the high lateral diffusion of the buried collector region. Moreover very thick epitaxial growths are necessary because allowance must also be made for rising of the antimony to the surface; yields are thus penalized because of the quality of the epitaxial layer. In addition there arise considerable difficulties of alignment of the subsequent photomaskings because plotting topographies through the thick epitaxial layers is a source of problems.
Moreover, implantation of high quantities of phosphorous (even higher than 10.sup.15 atom/cm.sup.2) then gives rise to a very high defect rate; among other things about half of the dopant introduced diffuses to the substrate and is thus unused.
Finally, because of the thermal cycles necessary for manufacturing the device, the transition between the epitaxial and diffused collector regions is not sharp, but displays a trend with a low dC/dX gradient of the concentration C of dopant along the depth X in the chip. This low dC/dX gradient has very unfavorable consequences for the series drain resistance (Ron) of a MOS power transistor (or the current-carrying capacity in the case of a bipolar power transistor).